Conventional semiconductor memory devices may include a memory cell array having a plurality of memory cells, which store data and a peripheral circuit which controls data input/output to/from the memory cell array. A static memory cell (e.g., SRAM cell) includes a plurality of transistors, and a dynamic memory cell (e.g., DRAM cell) includes one transistor and one capacitor. The peripheral circuit may include an inverter, a NAND gate and a NOR gate, where each of the gates includes transistors. In the typical memory cell and peripheral circuit, all of a plurality of transistors are arranged on the same layer above a semiconductor substrate. Thus, as the capacity of the memory cell array (i.e., the number of the memory cells) is increased, the layout area size is also increased, which may lead to large chip size.
For the foregoing reason, research has been performed to reduce the layout area size even as a capacity of the memory cell array is increased. For example, a method of reducing layout area size of the memory cell array by stacking transistors in a memory cell has been introduced (see, e.g., FIGS. 5A and 6A).
However, if layout area size of the peripheral circuit as well as layout area size of the memory cell array is reduced, the total area size of the semiconductor memory device can be reduced as much. Besides, as transistors that form the memory cell are stacked, the transistors, which form the memory cell, should have different structure.